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MPC962308D-1R2 - 3.3 V Zero Delay Buffer PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16

MPC962308D-1R2_3866694.PDF Datasheet

 
Part No. MPC962308D-1R2 MPC962308D-2R2 MPC962308D-3R2
Description 3.3 V Zero Delay Buffer PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16

File Size 445.68K  /  12 Page  

Maker

Motorola Mobility Holdings, Inc.



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Part: MPC962308D-1
Maker: Freescale Semiconductor
Pack: ETC
Stock: Reserved
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 Full text search : 3.3 V Zero Delay Buffer PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16


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Delay 45 /-2.3 ns, fixed SIP delay line Td/Tr=5
Delay 40 /-2 ns, fixed SIP delay line Td/Tr=5
Delay 270 /-13.5 ns, fixed SIP delay line Td/Tr=5
Delay 25 /-1.3 ns, fixed SIP delay line Td/Tr=5
Delay 170 /-8.5 ns, fixed SIP delay line Td/Tr=5
Delay 120 /-6 ns, fixed SIP delay line Td/Tr=5
Delay 10 /-1 ns, fixed SIP delay line Td/Tr=5
Delay 90 /-4.5 ns, fixed SIP delay line Td/Tr=5
Delay 70 /-3.5 ns, fixed SIP delay line Td/Tr=5
Delay 130 /-6.5 ns, fixed SIP delay line Td/Tr=5
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Delay 3.5 /-1 ns, fixed SIP delay line Td/Tr=5
Delay 100 /-5 ns, fixed SIP delay line Td/Tr=5
Delay 105 /-5.3 ns, fixed SIP delay line Td/Tr=5
Delay 140 /-7 ns, fixed SIP delay line Td/Tr=5
Delay 150 /-7.5 ns, fixed SIP delay line Td/Tr=5
Delay 15 /-1 ns, fixed SIP delay line Td/Tr=5
Delay 20 /-1 ns, fixed SIP delay line Td/Tr=5
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Delay 30 /-1.5 ns, fixed SIP delay line Td/Tr=5
Delay 37.5 /-1.9 ns, fixed SIP delay line Td/Tr=5
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